Untitled Document
 
Untitled Document
 
You may need to enable or update / install Adobe Flash Player Plug-in to display JPE e-Book in your device properly. If you use Google Chrome, please find information here
> Archives > Current Issues
JPE, Vol. 19, No. 4, July 2019
New Generalized PWM Schemes for Multilevel Inverters Providing Zero Common-Mode Voltage and Low Current Distortion
Nho-Van Nguyen and Tam-Khanh Tu Nguyen
Area High Power Converters
Abstract This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.
Keyword Common-mode voltage,Current ripple,Harmonic distortion,Multilevel inverter,Pulse width modulation (PWM),PWM inverters,PWM sequences
PDF
Full-text
Untitled Document