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JPE, Vol. 19, No. 3, May 2019
Pulse-Width Modulation Strategy for Common Mode Voltage Elimination with Reduced Common Mode Voltage Spikes in Multilevel Inverters with Extension to Over-Modulation Mode
Khoa-Dang Pham and Nho-Van Nguyen
Area High Power Converters
Abstract This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.
Keyword Cascaded inverter,Common mode voltage (CMV),Multilevel inverter,Neutral point clamped (NPC),Pulse-width modulation (PWM),Spikes
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