Untitled Document
Untitled Document
You may need to enable or update / install Adobe Flash Player Plug-in to display JPE e-Book in your device properly. If you use Google Chrome, please find information here
> Archives > Current Issues
JPE, Vol. 17, No. 1, January 2017
Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids
Kai Li, An Bo, Hong Zheng, and Ningbo Sun
Area Power Quality and Utility Application
Abstract This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.
Keyword Distorted grid,Small-signal model,Three-phase phase-locked loop,Unbalanced grid
Untitled Document